• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a digital/analog converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)−th capacitor has a unit capacitance, and a 2k−th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)−th capacitor is connected to a first terminal of the 2k−th capacitor. Also, if m is 1, 2, . . . , n−1, an m−th coupling capacitor is connected between the first terminal of the 2m−th capacitor and the first terminal of the (2m+t)−th capacitor, while an (n−1)−th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′−th one of coupling capacitor has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)−th coupling capacitors. Each of the analog switches is responsive to one of the 2n input digital data and is connected between a second terminal of one of the capacitors and two power supply sources.
    公开号:US20010002819A1
    申请号:US09/726,309
    申请日:2000-12-01
    公开日:2001-06-07
    发明作者:Naoyasu Ikeda
    申请人:NEC Corp；
    IPC主号:H03M1-68
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to a digital/analog (D/A) converter using capacitors. [0002]
    [0003] 2. Description of the Related Art [0003]
    [0004] In order to decrease the occupied area while the resolution is high, capacitance type D/A converters have been developed. [0004]
    [0005] A first prior art D/A converter is constructed by capacitors having binary weighted capacitance that are connected to an output terminal. Also, analog switches are provided that are controlled by input digital data connected to the capacitors. Each of the analog switches applies a low reference voltage or a high reference voltage to the corresponding capacitor in accordance with the corresponding input digital data. Thus, the first prior art D/A converter can generate an analog voltage in accordance with the input digital data (see JP-A-63-67920). This will be explained later in detail. [0005]
    [0006] In the above-mentioned first prior art D/A converter, however, since the total capacitance of the capacitors is still large. Thus, the occupied area is still large. [0006]
    [0007] In second and third prior art D/A converters, in order to more decrease the total capacitance, coupling capacitors are added to the first prior art D/A converters (see JP-A-57-124933 & JP-A-4-72819). This also will be explained later in detail. [0007]
    [0008] In the above-mentioned second and third prior art D/A converters, however, the total capacitance is still large, which would increase the occupied area. [0008] SUMMARY OF THE INVENTION
    [0009] It is object of the present invention to provide a capacitance type D/A converter capable of further decreasing the total capacitance. [0009]
    [0010] According to the present invention, in a D/A converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , 2n capacitors, (n−1) coupling capacitors and 2n analog switches are provided. If k is 1, 2, . . . , n, a (2k−1)−th capacitor has a unit capacitance, and a 2k−th capacitor has a capacitance twice the unit capacitance. A first terminal of the (2k−1)−th capacitor is connected to a first terminal of the 2k−th capacitor. Also, if m is 1, 2, . . . , n−1, an m−th coupling capacitor is connected between the first terminal of the 2m−th capacitor and the first terminal of the (2m+1)−th capacitor, while an (n−1)−th coupling capacitor is connected to the output terminal. If m′ is 2, 3, . . . , n−1, the first coupling capacitor has the unit capacitance, and an m′−th one of coupling capacitors has a capacitance of the unit capacitance plus a quarter of the capacitance of an (m′−1)−th coupling capacitor. Each of the analog switches is responsive to one of the [0010] 2n input digital data and is connected between a second terminal of one of the capacitors and two power supply sources.
    [0011] Note that, if the 2n−th capacitor and the 2n−th analog switch are omitted, the D/A converter serves as a (2n−1)-bit D/A converter. [0011] BRIEF DESCRIPTION OF THE DRAWINGS
    [0012] The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: [0012]
    [0013] FIG. 1 is a circuit diagram illustrating a first prior art 6-bit D/A converter; [0013]
    [0014] FIG. 2 is a circuit diagram illustrating a second prior art 6-bit D/A converter; [0014]
    [0015] FIG. 3 is a circuit diagram illustrating a third prior art 6-bit D/A converter; [0015]
    [0016] FIG. 4 is a circuit diagram illustrating an embodiment of the D/A converter according to the present invention; [0016]
    [0017] FIG. 5 is a diagram showing the relationship between the input digital data and the output voltage of FIG. 4; [0017]
    [0018] FIG. 6 is a circuit diagram illustrating a modification of the D/A converter of FIG. 4; [0018]
    [0019] FIG. 7 is a diagram showing the relationship between the input digital data and the output voltage of FIG. 6; [0019]
    [0020] FIG. 8 is a circuit diagram illustrating a generalized D/A converter from the D/A converter of FIG. 4; [0020]
    [0021] FIGS. 9 and 10 are circuit diagrams for explaining the operation of the D/A converter of FIG. 8; and [0021]
    [0022] FIG. 11 is a circuit diagram illustrating a generalized D/A converter from the D/A converter of FIG. 6. [0022] DESCRIPTION OF THE PREFERRED EMBODIMENT
    [0023] Before the description of the preferred embodiment, prior art D/A converters will be explained with reference to FIGS. 1, 2 and [0023] 3.
    [0024] In FIG. 1, which illustrates a first prior art 6-bit D/A converter (see JP-A-63-67920), capacitors C[0024] 0, C1, . . . , C5 having binary weighted capacitance such as 1pF, 2pF, . . . , 32pF, respectively, are connected to an output terminal OUT where voltage is VOUT. Also, analog switches SW0, SW2, . . . , SW5 controlled by 6-bit input digital data D0, D1, . . . , D5 are connected to the capacitors C0, C1, . . . , C5, respectively. Each of the analog switches SW0, SW1, . . . , SW5 applies a reference voltage VL or VH to the corresponding capacitor in accordance with the corresponding input digital data.
    [0025] For example, if (D[0025] 0, D1, D2, D3, D4, D5)=(0, 0, 0, 0, 0, 0), the analog switches SW0, SW1, . . . , SW5 apply the reference voltage VL to the capacitors C0, C1, . . . , C5, respectively, so that the output voltage VOUT is
    [0026] Also, if (D[0026] 0, D1, D2, D3, D4, D5)=(1, 0, 0, 0, 0, 0), the analog switch SW0 applies the reference voltage VL to the capacitor C0 while the analog switches SW1, SW2, . . . , SW5 apply the reference voltage VH to the capacitors C1, C2, . . . , C5, so that the output voltage VOUT is
    [0027] Further, if (D[0027] 0, D1, D2, D3, D4, D5)=(1, 1, 1, 1, 1, 1), the analog switches SW0, SW1, . . . , SW5 apply the reference voltage VH to the capacitors C0, C1, . . . , C5, so that the output voltage VOUT is
    [0028] Thus, the D/A converter of FIG. 1 can generate an analog voltage V[0028] OUT in accordance with the 6-bit input digital data (D0, D1, . . . , D5).
    [0029] In the D/A converter of FIG. 1, since use is made of binary weighted capacitors, the occupied area can be decreased and the resolution can be higher as compared with conventional resistor string type D/A converters. [0029]
    [0030] In the D/A converter of FIG. 1, however, the total capacitance C[0030] TOTAL of the capacitors C0, C1, . . . , C5 is 63pF and is still large. Note that if the number of the capacitors is n, the total capacitance CTOTAL thereof is represented by
    [0031] where the capacitance of the capacitor C[0031] 0 is 1pF. Thus, the occupied area is still large.
    [0032] In FIG. 2, which illustrates a second prior art 6-bit D/A converter (see JP-A-57-124933), a coupling capacitor CC having a capacitance of 1pF is added to the elements of FIG. 1, and the capacitances of the capacitors C[0032] 3, C4 and C5 are 1pF, 2pF and 4pF, respectively. The operation of the D/A converter of FIG. 2 is the same as that of the D/A converter of FIG. 1.
    [0033] In the D/A converter of FIG. 2, the total capacitance C[0033] TOTAL of the capacitors C0, C1, . . . , C5 as well as the coupling capacitor CC is 15pF and is smaller than that of the D/A converter of FIG. 1.
    [0034] In FIG. 3, which illustrates a third prior art 6-bit D/A converter (see JP-A-4-72819), coupling capacitors CC[0034] 1, CC2, . . . , CC5 having a capacitance of 1pF are added to the elements of FIG. 1, and the capacitances of the capacitors C0, C1, C2, C3, C4 and C5 are 1pF. The operation of the D/A converter of FIG. 3 is the same as that of the D/A converter FIG. 1.
    [0035] In the D/A converter of FIG. 3, the total capacitance C[0035] TOTAL of the capacitors C0, C1, . . . , C5 as well as the coupling capacitors CC1, CC2, CC3, CC4 and CC5 is 16pF and is smaller than that of the D/A converter of FIG. 1.
    [0036] In the D/A converters of FIGS. 2 and 3, however, the total capacitance C[0036] TOTAL is still large, which would increase the occupied area.
    [0037] In FIG. 4, which illustrates an embodiment of the D/A converter according to the present invention, coupling capacitors CC[0037] 1 and CC2 having capacitances of 1pF and 1.25pF, respectively, are added to the elements of FIG. 1, and the capacitance's of the capacitors C0, C1, C2, C3, C4 and C5 are 1pF, 2pF, 1pF, 2pF, 1pF and 2pF, respectively. The operation of the D/A converter of FIG. 4 is the same as that of the D/A converter of FIG. 5 which shows a relationship between the input digital data (D5, D4, D3, D2, D1, D0) and the output voltage VOUT where VL is OV and VH is 1V.
    [0038] In the D/A converter of FIG. 4, the total capacitance C[0038] TOTAL of the capacitors C0, C1, . . . , C5 as well as the coupling capacitors CC1 and CC2 is 11.25pF and is smaller than those of the D/A converter of FIGS. 1, 2 and 3, which would decrease the occupied area.
    [0039] In FIG. 6, which illustrates a modification of the D/A converter of FIG. 4, the D/A converter of FIG. 4 is applied to a 5-bit D/A converter where the capacitor C[0039] 5 and the analog switch SW5 of FIG. 4 are omitted. Note that the total capacitance CTOTAL of the D/A converter of FIG. 6 is smaller than that of the corresponding prior art D/A converter. In this case, FIG. 7 shows a relationship between the input digital data (D4, D3, D2, D1, D0) and the output voltage VOUT where VL is OV and VH is 1V.
    [0040] In FIG. 8, which illustrates a generalized (2n+2)-bit D/A converter from the D/A converter of FIG. 4, capacitors C[0040] 0, C1, C3, C4, . . . , C2n, C(2n+1) are provided where n is 1, 2, . . . in this case, the capacitance each of the capacitors C0, C2, . . . , C2n is 1pF which is a unit value or a minimum value, and the capacitance of each of the capacitors C1, C3, . . . , C(2n+1) is 2pF.
    [0041] A first terminal of the capacitor C[0041] 2k is connected to a first terminal of the capacitor C(2k+1) where k is 0, 1, . . . , n.
    [0042] Also, one coupling capacitor CCk is connected between the first terminals of the capacitors C(2k−2) and C(2k−1) where k is 0, 1, . . . , n. In this case, the capacitance of the coupling capacitor CCk is represented by [0042]
    [0043] where C is 1pF (unit value). [0043]
    [0044] Further, the coupling capacitor CCn is connected to an output terminal OUT whose voltage is V[0044] OUT.
    [0045] On the other hand, one analog switch SW(2k+1) is connected to a second terminal of the capacitor C(2k+1) where k is 0, 1, . . . , n. The analog switch SW(2k+1) is controlled by input digital data D(2k+1) to connect the second terminal of the capacitor C(2k+1) to either a power supply source PL or a power supply source PH. Note that the power supply sources PL and PH generate voltages V[0045] L and VH, respectively.
    [0046] If the D/A converter of FIG. 8 operates a D/A converter where V[0046] L is 0V and VH is 1V, a voltage E(n+1) equal to the output voltage VOUT has to satisfy the following equation:
    [0047] This equation (1) will be proved by using the following induction method. [0047]
    [0048] First, assume that n is 0. In this case, an equivalent circuit diagram of the D/A converter of FIG. 8 is illustrated in FIG. 9. That is, a voltage E[0048] 1 (D0) derived by the digital data D0 is
    [0049] Also, a voltage E[0049] 1(D1) derived by the digital data D1 is
    [0050] Therefore, from Thevenin's therem, [0050]
    [0051] Thus, the equation (1) where n=1 is proved. [0051]
    [0052] Next, assume that the equation (1) where n=k−1 is established, i.e., [0052]
    [0053] Next, consider that n is k+1 as illustrated in FIG. 10. In this case, a conductance C[0053] ok from a point whose voltage E(k+1) is given by
    [0054] Therefore, the voltage E(k+1) of FIG. 10 is calculated by [0054]
    [0055] Thus, from the equations (2), (3) and (4), [0055]
    [0056] Thus, the equation (1) has been proved. [0056]
    [0057] In FIG. 11, which illustrates a generalized (2n+1)-bit D/A converter from the D/A converter of FIG. 6, capacitors C[0057] 0, C1, C3, C4, . . . , C(2n−1), C2n are provided where n is 1, 2, . . . That is, the capacitor C(2n+1) and the analog switch SW(2n+1) of FIG. 8 are omitted. In this case, the equation (1) is replaced by
    [0058] As explained hereinabove, according to the present invention, since the total capacitance is small, the occupied area can be decreased. [0058]
    权利要求:
    Claims (2)
    [1" id="US-20010002819-A1-CLM-00001] 1. A digital/analog converter for converting 2n-bit input digital data into an analog output voltage where n is 2, 3, . . . , comprising:
    2n capacitors, a (2k−1)−th one of said capacitors having a unit capacitance, a 2k−th one of said capacitors having a capacitance twice said unit capacitance, a first terminal of said (2k−1)−th capacitor being connected to a first terminal of said 2k−th capacitor, where k is 1, 2, . . . , n;
    (n−1) coupling capacitors, an m−th one of said coupling capacitors being connected between the first terminal of said 2m−th capacitor and the first terminal of said (2m+1)−th capacitor, an (n−1)−th one of said coupling capacitors being connected to said output terminal, the first coupling capacitor having said unit capacitance, an m′−th one of coupling capacitors having a capacitance of said unit capacitance plus a quarter of the capacitance of an (m′−1)−th one of said coupling capacitors, where m is 1, 2, . . . , n−1 and m′ is 2, 3, . . . , n−1; and
    2n analog switches, each responsive to one of said 2n input digital data and connected between a second terminal of one of said capacitors and two power supply sources.
    [2" id="US-20010002819-A1-CLM-00002] 2. A digital/analog converter for converting (2n−1)-bit input digital data into an analog output voltage where n is 2, 3, . . . , comprising:
    (2n−1) capacitors, a (2k−1)−th one of said capacitors having a unit capacitance, a 2k−th one of said capacitors having a capacitance twice said unit capacitance, a first terminal of said (2k−1)−th capacitor being connected to a first terminal of said 2k−th capacitor, where k is 1, 2, n−1;
    (n−1) coupling capacitors, an m−th one of said coupling capacitors being connected between the first terminal of said 2m−th capacitor and the first terminal of said (2m+1)−th capacitor, an (n−1)−th one of said coupling capacitors being connected to said output terminal, the first coupling capacitor having said unit capacitance, an m′−th one of coupling capacitors having a capacitance of said unit capacitance plus a quarter of the capacitance of an (m′−1)−th one of said coupling capacitors, where m is 1, 2, . . . , n−1 and m′ is 2, 3, . . . , n−1; and
    (2n−1) analog switches, each responsive to one of said (2n−1) input digital data and connected between a second terminal of one of said capacitors and two power supply sources.
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    法律状态:
    2001-06-15| AS| Assignment|Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IKEDA, NAOYASU;REEL/FRAME:011903/0001 Effective date: 20001222 |
    2002-05-17| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-11-14| FPAY| Fee payment|Year of fee payment: 4 |
    2009-11-04| FPAY| Fee payment|Year of fee payment: 8 |
    2013-03-15| AS| Assignment|Owner name: GOLD CHARM LIMITED, SAMOA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:030015/0078 Effective date: 20121130 |
    2013-11-27| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    JP34327999A|JP3275966B2|1999-12-02|1999-12-02|Digital to analog converter|
    JP11-343279||1999-12-02||
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